Integrated circuit fabrication may include fabrication of features (e.g., conductive pillars) over and directly against semiconductor material surfaces. In some applications, it may be difficult to access such semiconductor material surfaces due to adjacent structures limiting access to the surfaces. For instance, passing digit lines may limit access to semiconductor surfaces which are to be accessed for coupling with charge-storage structures (e.g., capacitors) during fabrication of memory. The difficulty increases with increasing levels of integration. Also, even when the surfaces can be accessed, there may be poor overlap of the features with the surfaces and/or there may be poor adhesion of the features to the surfaces. It would be desirable to develop new methods of fabrication which overcome at least some of the difficulties associated with forming features over and directly against semiconductor surfaces.